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CPUID Instruction

The CPUID instruction (opcode 0FA2) allows software to inquire about the CPU vendor, family, model, stepping, features, and cache information.

The presence of the CPUID instruction is indicated by the ability to change the value of the ID Flag (bit 21) in the EFLAGS register.

The CPUID level is determined by the value placed in the EAX register before the instruction is executed. Each CPUID level returns different information in EAX, EBX, ECX, and EDX registers.

Standard Levels

CPUID Instruction with EAX = 0000 0000h
Standard level 0h (EAX = 0) of the CPUID instruction returns the maximum standard CPUID levels supported as well as the processor vendor string.

After the instruction is executed, the EAX register contains the maximum standard CPUID levels supported. The maximum standard CPUID level is the highest acceptable value for the EAX register input. This does not include the extended CPUID levels. The EBX through EDX registers contain the vendor string of the processor. Note that the registers are placed out of order.

Register Description
EAXMaximum Standard Levels
EBX-EDX-ECXVendor String - "CyrixInstead"

Description 6x86(L) M II* MediaGX MediaGX
MMX Enhanced
Max Std Levels1112

CPUID Instruction with EAX = 0000 0001h
Standard function 01h (EAX = 1) of the CPUID instruction returns the Processor Type, Family, Model, and Stepping information of the current processor in EAX. The EBX and ECX registers are reserved.

Register Description
EAX[3:0] Stepping ID
EAX[7:4] Model
EAX[11:8] Family
EAX[15:12] Type
EAX[31:16] Reserved

Description 6x86(L) M II* MediaGX MediaGX
MMX Enhanced
Stepping ID xxxxxxxx
Model 2044
Family 5645
Type 0000

The Standard Feature Flags supported are returned in the EDX register. Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features have protection control in CR4. Before using any of these features on the processor, the software should check the corresponding feature flag. Attempting to execute an unavailable feature can cause exceptions and unexpected behavior. For example, software must check bit 4 before attempting to use the Time Stamp Counter instruction.

Feature Flag EDX Bit CR4 Bit 6x86 6x86(L) M II* MediaGX MediaGX
MMX Enhanced
FPU On-chip0-xxxxx
Virtual Mode Extension10,1-----
Debugging Extension23-xx--
Page Size Extension34--x--
Time Stamp Counter42--x-x
RDMSR / WRMSR Instructions58--x-x
Physical Address Extension65-----
Machine Check Exception76-----
CMPXCHG8B Instruction8--xx-x
On-chip APIC Hardware9------
Undefined10------
SYSENTER / SYSEXIT Instructions11- -----
Memory Type Range Registers12------
Page Global Enable137--x--
Machine Check Architecture14------
Conditional Move Instruction15---x-x
Page Attribute Table16------
Undefined17-22------
MMX Instructions23---x-x
Fast FPU Save and Restore24------
Undefined25-31------

CPUID Instruction with EAX = 0000 0002h
Standard function 02h (EAX = 02h) of the CPUID instruction returns information that is specific to the Cyrix family of processors. Information about the TLB is returned in EAX. Information about the L1 Cache is returned in EDX. The EBX and ECX registers are reserved.

Register Description
EAX TLB Information
EBX Reserved
ECX Reserved
EDX L1 Cache Information

Value Description
xxxx70xxhTLB is 32 Entry, 4-way Set Associative, and has 4K Pages
xxxxxx01hThe CPUID instruction needs to be executed only once with an input value of 02h to retrieve complete information about the cache and TLB
xxxxxx80hL1 Cache is 16K, 4-way Set Associative, and has 16 Bytes per Line

Description MediaGX MMX Enhanced
EAX (TLB Info) 00007001h
EDX (L1 Cache Info) 00000080h


* For the CPUID registers listed herein, the M II contains identical CPUID information as the 6x86MX. For space constraints, only the M II is listed here. Please see the Cyrix CPU Detection Guide and the DIR1 register for information on differentiating the two processors.


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