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MCS®251 Microcontroller
8xC251SA/SB/SP/SQ Product Overview
The more powerful 8xC251SA/SB/SP/SQ has ALL of the 8xC151SA/SB architecture and peripheral features plus the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.

8xC251SA/SB/SP/SQ Block Diagram

  • New core architecture
  • Up to 15X performance increase using new MCS 251 microcontroller instructions
  • Significantly reduce RFI
  • Increase efficiency and support of C language programming
  • Binary code and pin compatible with MCS 51 microcontroller
  • Hardware investment protected
  • Reduce development time with backward compatible MCS 51 microcontroller instruction set
  • 8 Kbytes/16 Kbytes on-chip ROM/OTPROM or ROMless version
  • Flexibility in using different memory options in development and production
  • Programmable Counter Array (PCA) supports
    • Real-time capture and compare
    • High speed output
    • PWM
  • Flexibility and performance enhancement in real-time control applications such as:
    • Measurement of duty cycle, phase
      difference and frequency
    • Real-time interrupt generation and output toggling
    • Adjustable duty cycle generation
  • Hardware watchdog timer
  • Increased system reliability
  • Page mode configuration
  • Increases the performance for external instruction fetch by 2X
  • Programmable wait states (0-3) configuration and external wait pin capability
  • Flexibility in external memory and peripheral interface
  • Allows the use of either fast or slow memory
  • Support seven interrupt sources, each with four interrupt priority levels
  • Increased flexibility for event control applications
  • 256 Kbytes external memory space
  • Increased capability and flexibility to handle large software requirements
  • 512/1 Kbyte on-chip RAM
  • Increased internal memory capacity for data manipulation and C language support

[*] MCS®

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