When dealing with applications that use two external memory devices, the INST pin can be used to clarify from where code and data fetches are made. In doing so, a few work-arounds may be required. These work-arounds alleviate the problems of inadvertently fetching the CCB from an incorrect location, forcing interrupt vector fetches to the code space rather than data space, and working around the 196KC's TIJMP characteristics.
Before the workarounds are presented, it is important to discuss the behavior of the INST pin. The INST pin is used only when external memory is being accessed by the Program Counter. INST is high for the external memory instruction stream, including immediate data. INST remains low during all other external memory fetches. This also includes interrupt vector fetches and the 196KC's TIJMP TBASE address since those addresses do not come from the Program Counter. If the TIJMP INDEX points to external memory, that fetch occurs with INST low. The INST signal is guaranteed to be stable only during a bus cycle. Between bus cycles, it often goes low. It will be high when external memory is being addressed by the Program Counter and will be low otherwise. INST goes low during reads and writes of internal registers. Of course, there is no external RD# or WR# when these internal reads and writes occur. With the above characteristics taken into account, INST can be treated just like an address line for bank-switched program/data memories.
Upon power-up or reset, the CCB must be fetched from the correct location. Since the INST pin does allow both 64K of code space and 64K of data space, one must be sure that the CCB is fetched from code space. Otherwise, the Chip Configuration Byte (CCB) may be obtained from the data space where RAM may be located. The following circuit is a single-chip solution to the CCB problem:
One input of the latch is tied to the RESET# pin which sets the latch during power up. The other input to the latch is tied to the WR# pin which resets the latch as soon an the first external write occurs. Note that WR# occurs only at even addresses in 16-bit bus mode. A write to an odd address in 16-bit mode will not reset the latch. The NEWINST output will remain at a high level until the first external write occurs, thus forcing all external memory requests to access the code space memory during this initial time. Quite often, a PAL is used for control and address decoding in a system and thus, the above logic could simply be included in the PAL. A PAL could also be used to force all external memory requests in the address range of 2000H to 207FH to access code space. This would force the CCB fetch and the interrupt vector fetches to be done from external code space rather than from external data space. The PAL could be programmed to force all external memory accesses in the range of 2000H to 3FFFH to fetch from code memory. The TIJMP tables could be located in this section of memory.
When using interrupts and the TIJMP instruction, the following work-around applies. Even though interrupt vectors are typically located in code space, INST treats interrupt vector fetches as data. Similarly, the TBASE address in the TIJMP instruction does not come from the program counter so the INST signal is low for data. Hence, the easiest work-around for the interrupt vector problem and the TIJMP problem is to copy the interrupt vector table and the TIJMP table(s) into a block of data memory (RAM) during initialization of the system.
* Legal Information © 1999 Intel Corporation