ABSTRACT:
This TechBit describes how to implement a 2-pole, 4-pole and 6-pole IIR filter using the 80C196KC Eval Board.
Introduction
Digital Signal Processing (DSP) is the technique of using digital devices to process continuous signals or data, often in real-time. Historically, many of these functions were performed using analog techniques. DSP is NOT an architecture although many architectures have been designed and optimized for DSP-type algorithms. In fact, any microcontroller, microcomputer, microprocessor or PC can perform DSP applications, given enough time and/or a sufficiently high clock frequency. It would be surprising to find any present-day microcontroller that could not manage to implement a 10 Hz low-pass filter function.
DSP techniques are used in a multitude of applications of which digital filters, motor control, speech recognition and synthesis, video processing, waveform generation, spectrum analysis, pattern matching, radar/sonar processing, missile guidance, and modems are just a few. Each generation of higher-speed devices opens new applications for DSP techniques.
DSP algorithms are associated with a discrete time interval between input samples. When one designs an LC filter, one can use a Laplace transform to determine the continuous time frequency response. The corresponding discrete time transform is called the Z transform and depends upon discrete samples of the input spaced equally in time. DSP algorithms invariably require a sum of products calculation and the time it takes to do a MAC (multiply and accumulate) function is of primary importance. This MAC function often also includes automatically moving data down a pipeline. Architectures optimized for DSP applications sport MAC times ranging down to AT&T's DSP16A at 25 nS and the magnitude faster TMS320C8x. An average microcontroller takes a dozen or more clock cycles for a multiply which limits the maximum frequency capable of being processed using DSP techniques. New members of the Intel `C196 family with much higher throughputs and DSP characteristics will be introduced in 1994 and 1995, according to an electronics magazine interview.
One of the many applications of DSP techniques is digital filters. This TechBit will describe digital filtering techniques used with the 'C196 microcontroller. Numerous publications and references are available on digital filters. The textbooks and digital filter design software used to generate this TechBit are listed in the appendix.
Digital Filters
Digital filter theory spans a range from complicated to esoteric. This paper will concentrate on linear time-invariant filters which can be described by the following convolution:
These are complex functions and convolution of complex functions is not something one would normally choose to do with a 'C196. Fortunately, performing the Z transform on the above equation yields a result more suited to microcontroller operations, namely multiplication. Using the Z transform on the filter characteristic equation maps the function from the infinite time domain to the repeating frequency domain. Convolution in the time domain implies multiplication in the frequency domain. The remapped characteristics can then be associated with a unit circle of radius one having a real horizontal axis and an imaginary vertical axis. Expressing the above relationship in terms of the corresponding Z transforms yields:
The poles signify amplification at certain frequencies (angles) and the zeros signify attenuation at certain frequencies. The sample frequency corresponds to 360o. Knowing the poles and zeros of the function allows the designer to calculate the coefficients used in the actual microcontroller algorithm. It is possible to reinvent the wheel by taking a brute force approach to filter design but it is much more productive to use one of the handbooks of filter design or, better yet, one of the available filter design software packages.
Common Filter Algorithms
There are two commonly implemented digital filters, the finite-impulse-response (FIR) and the infinite-impulse-response (IIR) filter. FIR filters are more stable than IIR filters because the output normally depends only on past inputs (not on past outputs) and it is easily constrained to produce a linear phase response. IIR filters can be unstable and produce a phase shift from input to output because past outputs as well as past inputs can affect the present output.
When does one use an FIR design and when does one use an IIR design? If stability and linear phase response is required, the FIR is the filter of choice. If phase shift is not a factor, an IIR filter can be implemented with fewer number of poles and therefore consume less software execution time. The number of poles is proportional to the number of MACs needed in the filter algorithm. For instance, a particular IIR filter requiring 4 poles may require 28 poles in an FIR implementation thereby consuming seven times the processing power. In general, if a 'C196 application can be done with an IIR filter, it probably should be.
There are a number of networks that are used to represent the stages of the filter. The most common are the cascade form for IIR filters and the parallel form for FIR filters. There are two types of each of these forms, named form I and form II. A structure is called canonical when it implements the smallest possible number of delays, adders, and multipliers.
It is beyond the scope of this TechBit to cover the theory and choices available to the digital filter designer. For IIR filter designs, one must choose between Bilinear Transformation and Impulse Invariance along with a type of filter such as, Butterworth, Tschebyscheff, Elliptic, or Bessel, each of which has varying characteristics. For FIR filter designs, one must choose from a number of windowing techniques including Rectangular, Triangular, Hanning, Hamming, Blackman, Kaiser, or equiripple. Since the purpose of this TechBit is to demonstrate the capabilities of the 'C196 as a digital filter, the approach that yields the fewest calculations was taken. Thus the choice of the IIR filter, Bilinear Transformation, and cascade representations.
In the cascade form, the Z transform is represented by a number of quadratic equations multiplied by each other in both the numerator and the denominator. Each numerator and denominator pair of quadratic equations take one cascade stage of two poles to implement. Assume a particular two-pole IIR filter with the following Z transform:
Single Stage, Two Pole Cascade Form II
For each input sample the following high-level language program segment illustrates the cascade form II filter structure. Note the repeated MAC (multiply and accumulate).
Using a Filter Design Program
Numerous filter design programs are available and a few are in the public domain. This TechBit makes no attempt to compare different programs or recommend one over another. Anything a filter design program can do, a knowledgable engineer with a scientific calculator and a digital filter design handbook can accomplish.
The first step in using a filter design program is to initialize it to the particular processor that is being used. The 'C196 is a 16-bit, fixed-point processor and that information is entered into the filter design program. Other possibilities are eight-bit, 24-bit, 32-bit, and floating point.
The next step is to enter the parameters of the particular filter desired. One possibility is an IIR filter with a sample rate of 1 KHz, a passband of 400-410 Hz, a lower stopband of 200 Hz, and an upper stopband of 490 Hz. We will allow 1 dB of ripple within the passband and frequencies outside the stopband must have an attentuation of 20 dB. This information is entered into the filter design program and, as if by magic, everything one needs to implement the filter is created by the filter design software.
The numbers themselves are normalized to less than one to avoid overflow. But some of the actual values of the coefficients may be greater than one. When this condition occurs, a combination of values less than one and shifts are used where one shift left is the same as multiplying by two and two shifts right is the same as dividing by 4, etc. The input value is also scaled before any operation occurs. The scaling value is the gain of the preamplifier. The following is a copy of the output from the filter design program.
1 0001h shift count for section 1 values
14642 3932h 0.89372125 section 1 coefficient B0
0 0000h 0.00000000 section 1 coefficient B1
14642 C6CEh -0.89372125 section 1 coefficient B2
25536 9C40h -1.5586358 section 1 coefficient A1
14476 C774h -0.88357312 section 1 coefficient A2
All numbers associated with the digital filter will be signed hexadecimal fractional numbers between the values of -0.9999695 (8000H) and +0.9999695 (7FFFH). 0000H is zero, 0001H is +0.00003051758 (1/32768), and FFFFH is -0.00003051758.
A sine-wave signal generator was connected to JP1-2 (Analog Channel 0) and JP1-1 (ANGND-1) on the 'C196KC Eval Board and adjusted to span 0 v (min) to 5.12 v (max). The A/D converter output is 0000H for 0 volts input and FFC0H for 5.12 volts input. Around 2.56 volts the output changes from 7FC0H to 8000H at half-scale. It would be ideal if the A/D output would go from -1/512 to zero to +1/512 around 2.56 volts and a simple mathematical trick accomplishes that feat. Simply toggling the sign bit normalizes the A/D output to match the signed hexadecimal fractions that exist in the rest of the filter software.
One other characteristic to notice is that when a signed hexadecimal (1.15) fractional multiplication is done the result contains two sign bits (2.30). For instance, multiplying 1/2 (4000H = 214) by 1/2 yields 10000000H = 228 which in signed hexadecimal fractional notation would be 1/8 instead of the required 1/4. To remedy the problem we simply shift left to rid ourselves of one of the sign bits (and multiply our result by two) to obtain the correct fractional value. (2.30 becomes 1.30)
One nice characteristic of these types of filters is that the frequency response varies linearly with the sample frequency. The 400-410 Hz bandpass filter becomes a 40-41 Hz bandpass filter if the sample rate is changed from 1000 Hz to 100 Hz. With a sample rate of 20 KHz, the bandpass response is 8-8. 2 KHz. Thus a standardized set of filters can be designed and tuned to the required frequency by adjusting the sample frequency. An important principle of digital filter sampling rate is the Nyquist frequency or rate. The Nyquist Theorum states that the sampling rate must be greater than twice the signal bandwidth. For our bandpass application it means the sampling frequency must be more than twice the upper bandstop frequency. The 1000 Hz sampling frequency is more than twice the upper bandstop frequency of 490 Hz so we meet the requirements. The phenomenon that occurs when this sampling rule is violated is called aliasing and results in a filter responding to other frequencies as if they were our bandpass center frequency of 405 Hz. The following graph illustrates aliasing (at 595 Hz, 1405 Hz, and 1595 Hz) and indicates that our digital filter should not be exposed to frequencies above 500 Hz. If these higher frequencies may be encountered, then a low-pass analog filter should be installed ahead of our digital bandpass filter.
Bandpass Filter designed for a center frequency of 405 Hz.
Graph indicates aliasing at 595 Hz, 1405 Hz, and 1595 Hz.
The filters in this TechBit were developed to run on an 80C196KC Eval Board running at 16 MHz. In order to obtain an analog output that could be viewed on an oscilloscope, an MC1408 D/A converter was mounted on an external breadboard and interfaced to Port 1 through the JP2 connector. Assuming that the A/D converter has interrupted the program and has a digitized value waiting in the A/D Result Register, the resulting 8xC196 interrupt subroutine for the above filter is:
FILTER: | |
PUSHF | |
ADD | M00,AD_RESULT,#8000H ; CHANGE SIGN |
LDB | AD_COMMAND,#00H ; START HSO,A/D |
LDB | HSO_COMMAND,#0FH ; TIMER1,A/D |
ADD | HSO_TIME,TIMER1,#COUNT |
MUL | MUL_RESULT,M00,GAIN |
SHRAL | MUL_RESULT,#SHG-1 |
LD | M01,MUL_RESULT+2 |
MUL | MUL_RESULT,M11,A11 |
SHLL | MUL_RESULT,#SH1+1 |
ADD | M01,MUL_RESULT+2 |
MUL | MUL_RESULT,M21,A21 |
SHLL | MUL_RESULT,#SH1+1 |
ADD | M01,MUL_RESULT+2 |
MUL | MUL_RESULT,M01,B01 |
SHLL | MUL_RESULT,#SH1+1 |
LD | M02,MUL_RESULT+2 |
MUL | MUL_RESULT,M11,B11 |
SHLL | MUL_RESULT,#SH1+1 |
ADD | M02,MUL_RESULT+2 |
MUL | MUL_RESULT,M21,B21 |
SHLL | MUL_RESULT,#SH1+1 |
ADD | M02,MUL_RESULT+2 |
LD | M21,M11 |
LD | M11,M01 |
ADDB | PORT1,M02+1,#80H ; D/A OUT |
POPF | |
RET |
The A/D must be triggered at the sample rate of 1000 Hz. It is very important that the samples from the A/D be equally spaced in time. This can easily be done using the HSO unit and Timer1. At 16 MHz, Timer1 ticks every one uS and it takes the A/D converter 19.56 uS to complete a conversion. 19.56 uS is 19.56 ticks. To get a 1000 Hz sample rate, we must start an A/D conversion every 1000 uS which is 1000 ticks. We load Timer1 with 1000 minus 27 (A/D conversion plus interrupt latency time) or 973. Note that the automatic triggering of the A/D function using the HSO hardware gives equally spaced sample times vs triggering the A/D from a software loop or under interrupt control which yields sample times that are not as equally spaced. After setting up the HSO and A/D, we simply go into a loop waiting for an interrupt.
HERE:
SJMP HERE ; wait for interrupt
Obviously, when a digital filter is implemented in a system, the software will be performing other tasks until it is interrupted by the A/D. If the D/A converter is used to generate an output waveform, interrupts should be disabled during the digital filter interrupt routine so that a constant input and output sample time is maintained.
Optimizing 80C196 Code for Speed
One can see that a Digital Filter can consume a lot of 'C196 processor time. Some options exist for speeding up the operation. In the first program (IIR2P), B11 is a zero so lines 90-92 can be deleted. Also, since one three-operand ADD instruction is faster than two two-operand Add instructions, it would speed things up somewhat to have a MUL_RESULT1 and a MUL_RESULT2 and replace the two two-operand ADDs with a single three-operand ADD whenever possible. For instance, lines 81-86 can be speeded-up through the following combination: (Note that lines 78-80 would have to come after the following.)
MUL MUL_RESULT1,M11,A11
SHLL MUL_RESULT1,#SH1+1
MUL MUL_RESULT2,M21,A21
SHLL MUL_RESULT2,#SH1+1
ADD M01,MUL_RESULT1+2,MUL_RESULT2+2
The above ideas were used to modify IIR2PKC into IIR2POKC (see appendix) which also was modified to run full speed rather than under interrupt control. Running in this as fast as possible mode, the sampling frequency is 48 KHz which was 37% faster than the original IIR2P maximum sampling frequency of 35 KHz. From the Nyquist Theorum, we can say that the absolute maximum stopband frequency for a 16 MHz 'C196 is 24 Khz. (This gives a maximum possible passband frequency of 19 Khz for our 20 dB bandpass filter.)
Throughput With Digital Filters
A single two-pole filter running under interrupt control with a sample rate of 1000 Hz consumes 3% of the 16 MHz 'C196KC's processing power. Eight of these filters running concurrently (one for each A/D input) would consume 23% of the C196KC's time. A single two-pole filter running with a sample rate of 40 KHz would completely consume the processing power of a 16 MHz 80C196. The time it takes to do an A/D conversion is almost exactly the time it takes to execute a two-pole filter routine so the next digitized value is available by the time that we need it.
There is approximately 9 uS of fixed overhead and each set of two poles takes an additional 20 uS when running under interrupt control. Running a tight loop as fast as possible (no interrupts, no polling), the maximum sample rate for a two-pole (20 dB) filter is 40 KHz, for a four-pole (40 db) filter it is 21 KHz, and for a six-pole (80 dB) filter it is 15 KHz. Running under interrupt control at the 1000 Hz sample rate of the filters in this TechBit a 20 dB filter takes 1/35 of the processor's time, a 40 dB filter takes 1/20 and an 80 dB filter takes 1/15. From the Nyquist Theorum, we can say that the upper limit stopband frequency would be 17 Khz for a two-pole filter, 10 Khz for a four-pole filter, and 7 Khz for a six-pole filter running as fast as possible.
A D/A converter was attached to the 'C196KC Eval Board to observe the output on an oscilloscope. This is only one possibility of what to do with the output. Another approach would be to keep a running average of the absolute value of the output (DFT or FFT). Setting an appropriate threshold would allow for simple detection of the existence of the desired frequency. The filter software will output to the D/A converter if D_TO_A (IIR2P listing, line 7) is set equal to 1. If D_TO_A is set to any other value (eg. 0 on line 12) then the absolute value from the filter output is displayed in the Port 1 LEDs on the 'C196KC Eval Board.
Appendix
The theory presented in this TechBit comes primarily from:
Digital Filters and Signal Processing, Second Edition, by Leland B. Jackson, published by Kluwer Academic Publishers, 101 Philip Dr., Assinippi Park, Norwell, Ma. 02061.
Introduction to Digital Signal Processing, by Roman Kuc, published by McGraw-Hill.
The filter coefficient files were generated by a digital filter design software package, Filter Design and Analysis System, available from Momentum Data Systems, Inc., 1520 Nutmeg Place, Suite 108, Costa Mesa, Ca. 92626, (714)557-6884.
The Appendix includes:
* Legal Information © 1999 Intel Corporation