8XC196NT/NP: BR/EBR Instruction Execution

Description:

The B ranch Indirect (BR) and Extended Branch Indirect (EBR) instruction use the same opcode (E3h) to reduce the total number of opcodes for the 8XC196NT/NP. When using the BR instruction, the register used to store the branch address must be located at an eve n location, therefore the least significant bit of the register location must always be a 0. Since the least significant bit is a known value, this bit can be used to differentiate between the BR and EBR instructions. The following code demonstrates th e differences between the two cases:

 CASE 1: 
 rseg at 50h 
 tempword: dsw 1 
 
 cseg at 0ff2080h 
 

br [tempword] ;The compiler will generate `E350h cseg at 0ff5000h landhere: nop CASE 2: rseg at 50h tempword: dsl 1 cseg at 0ff2080h ld tempword,#8000h ld tempword+1,#0feh ebr [tempword] ;In this instance, the compiler will generate `E351h cseg at 0fe8000h landhere: nop

BR Execution:

Most non-extended instructions only operate within the same page. T he BR instruction is an exception to the rule. In 24-bit mode, if a BR instruction in page 01h is trying to branch to location 015000h (see example below), it will branch to location 0FF5000h instead. When using the BR instruction, the upper byte of the 24-bit program counter defaults to `FFh , which results in a branch to page FFh instead of the intended page. If one operates from a page other than FFh and wishes to branch within the same page, the EBR instruction should be used to make the branch corre ctly. The following example demonstrates this situation:

 rseg at 50h 
 tempword: dsw 1 
 
 cseg at 013000h 
 ld tempword, #5000h 
 br [tempword] 
 
 cseg at 015000h 
 not_here: nop 
 
 cseg at 0ff5000h 
 land_here: nop