Intel Architecture MMX^(TM) Technology

Chapter 1
INTRODUCTION TO THE INTEL ARCHITECTURE MMX^TM TECHNOLOGY DEVELOPER'S MANUAL

Intel's MMX ^TM technology is an extension to the Intel Architecture (IA) instruction set. The technology uses a single instruction, multiple data (SIMD) technique to speedup multimedia and communications software by processing multiple data elements in parallel. The MMX instruction set adds 57 new opcodes and a new 64-bit quadword data type. The new 64-bit data type, illustrated in Figure 1-1 below, holds packed integer values upon which MMX instructions operate.

Figure 1-1. New Data Types

In addition, there are eight new 64-bit MMX registers, each of which can be directly addressed using the register names MM0 to MM7. Figure 1-2 shows the layout of the eight new MMX registers.

Figure 1-2. MMX^TM Register Set

The MMX technology is operating-system transparent and 100% compatible with all existing Intel Architecture software; all applications will continue to run on processors with MMX technology. Additional information and details about the MMX instructions, data types and registers can be found in the Intel Architecture MMX^TM Technology Programmers Reference Manual (Order Number 243007).

MMX technology will give a large performance boost to many applications, such as motion video, combined graphics with video, image processing, audio synthesis, speech synthesis and compression, telephony, conferencing, 2D graphics, and 3D graphics. Almost any application which performs calculations on integer data in a repetitive and sequential manner can benefit from MMX technology. The performance improvement results from parallel processing of
8-bit, 16-bit and 32-bit data elements. An MMX instruction can operate on 8 bytes at once and two instructions can be executed in one clock cycle, which means that as many as 16 data elements can be processed in one clock cycle.

In addition to increased performance, MMX technology will free up additional processor cycles for other functions. Applications which previously needed extra hardware can now execute in software only. Lower processor usage allows better concurrency, a feature exploited in many of today's operating systems. Based on Intel's analysis, performance improvements range from 50% to 400% for certain functions. This magnitude of improvement is similar to the performance boost seen in moving to a new processor generation. In software kernels, much larger speedups have been observed, ranging from three to five times the original speed and beyond.

1.1 About This Manual

It is assumed that the reader is familiar with the Intel Architecture software model and assembly language programming.

This manual describes the software programming optimizations and considerations for the IA MMX technology. Additionally, it covers coding techniques and examples that will help you get started in coding your application.

This manual is organized into six chapters, including this chapter (Chapter 1), and one appendix.

Chapter 1-Introduction to the Intel Architecture MMX^TM Technology.

Chapter 2-Overview of Processor Architecture and Pipelines. This chapter provides an overview of the architecture and pipelines of Pentium® and dynamic (P6-family) processors with MMX technology.

Chapter 3-Guidelines for Developing MMX^TM Code. This chapter provides a list of rules and guidelines that will help you develop fast and efficient code. Additionally, it provides information on general optimization, instruction scheduling and selection, and cache and memory optimization.

Chapter 4-MMX^TM Code Development Strategy. This chapter reviews the steps for creating MMX routines in your application.

Chapter 5-Coding Techniques. This chapter contains coding examples to help you get started in coding MMX routines.

Chapter 6-Performance Monitoring Counters. This chapter details the performance monitoring counters and their functions.

Appendix A- MMX^TM Instruction Set. This appendix summarizes the MMX instructions.

1.2 Related Documentation

Refer to the following documentation for more information on the Intel Architecture and specific techniques referred to in this manual:

• Intel Architecture MMX ^TM Technology Programmers Reference Manual, Intel Corporation, Order Number 243007.
• Pentium® Processor Family Developer's Manual: Volume 1, 2, and 3, Intel Corporation, Order Number 241428, 241429, and 241430.
• Pentium® Pro Processor Family Developer's Manual: Volume 1, 2, and 3, Order Number 242690, 242691, and 242692.
• Optimizations for Intel's 32-bit Processors, Application Note AP-526, Order Number 242816