![[Intel Navigation Header]](/pix/header.gif){kind=small}
Intel Architecture MMX(TM) Technology
APPENDIX A
IA MMX™ INSTRUCTION SET SUMMARY
Table A1 summarizes the IA MMX™ instruction set base mnemonics. The instructions are grouped by categories of related functions.
Most of the instructions have multiple variations that are not listed in Table A1. For example, PADD has the following variations: PADDB, PADDW, and PADDD. The instruction variations and mnemonics are detailed in the Instruction description section of Chapter 5.
| Table A-1. IA MMX Instruction Set Summary, Grouped into Functional Categories | |||||
| Category | Wraparound | Signed Saturation | Unsigned Saturation | ||
| Arithmetic | addition | PADD | PADDS | PADDUS | |
| subtraction | PSUB | PSUBS | PSUBUS | ||
| multiplication | PMULL/H | ||||
| multiply and add | PMADD | ||||
| Comparison | compare | PCMPEQ | |||
| compare | PCMPGT | ||||
| Conversion | pack | PACKSS | PACKUS | ||
| unpack | PUNPCKL/H | ||||
| Packed | Full 64-bit | ||||
| Logical | and | PAND | |||
| and not | PANDN | ||||
| or | POR | ||||
| exclusive or | PXOR | ||||
| Shift | shift left logical | PSLL | PSLL | ||
| shift right logical | PSLL | PSLL | |||
| shift right arithmetic | PSRA | ||||
| 32-bit Transfers | 64-bit Transfers | ||||
| Data Transfer Operations | register--register | MOVD | MOVQ | ||
| load from memory | MOVD | MOVQ | |||
| store to memory | MOVD | MOVQ | |||
| FP and MMX(TM) State Management | EMMS | ||||