[Intel Navigation Header]

Intel Architecture MMX(TM) Technology


APPENDIX C
ALPHABETICAL LIST OF IA MMX™ INSTRUCTION SET MNEMONICS

The following table lists the mnemonics of the IA MMX™ instructions in alphabetical order. For each mnemonic, it summarizes the type of source data, the encoding of the first and second bytes in hexadecimal, and the format used.

Table C­ IA MMX™ Instruction Set Mnemonics
MNEMONIC
OPERAND TYPES
Byte 1
Byte 2
Byte 3, [4]
EMMSNone 0F77 mod-rm, [sib]
MOVDregister, memory/iregister 0F6E mod-rm, [sib]
MOVDmemory/iregister, register 0F7E mod-rm, [sib]
MOVQregister, memory/register 0F6F mod-rm, [sib]
MOVQmemory/register, register 0F7F mod-rm, [sib]
PACKSSDWregister, memory/register 0F6B mod-rm, [sib]
PACKSSWBregister, memory/register 0F63 mod-rm, [sib]
PACKUSWBregister, memory/register 0F67 mod-rm, [sib]
PADDBregister, memory/register 0FFC mod-rm, [sib]
PADDDregister, memory/register 0FFE mod-rm, [sib]
PADDSBregister, memory/register 0FEC mod-rm, [sib]
PADDSWregister, memory/register 0FED mod-rm, [sib]
PADDUSBregister, memory/register 0FDC mod-rm, [sib]
PADDUSWregister, memory/register 0FDD mod-rm, [sib]
PADDWregister, memory/register 0FFD mod-rm, [sib]
PANDregister, memory/register 0FDB mod-rm, [sib]
PANDNregister, memory/register 0FDF mod-rm, [sib]
PCMPEQBregister, memory/register 0F74 mod-rm, [sib]
PCMPEQDregister, memory/register 0F76 mod-rm, [sib]




Table C­1. IA MMX™ Instruction Set Mnemonics (Contd.)
MNEMONIC
OPERAND TYPES
Byte 1
Byte 2
Byte 3, [4]
PCMPEQWregister, memory/register 0F75 mod-rm, [sib]
PCMPGTBregister, memory/register 0F64 mod-rm, [sib]
PCMPGTDregister, memory/register 0F66 mod-rm, [sib]
PCMPGTWregister, memory/register 0F65 mod-rm, [sib]
PMADDWDregister, memory/register 0FF5 mod-rm, [sib]
PMULHWregister, memory/register 0FE5 mod-rm, [sib]
PMULLWregister, memory/register0FD5 mod-rm, [sib]
PORregister, memory/register 0FEB mod-rm, [sib]
PSHIMD*register, immediate 0F72 mod-rm, imm
PSHIMQ*register, immediate 0F73 mod-rm, imm
PSHIMW*register, immediate 0F71 mod-rm, imm
PSLLDregister, memory/register0FF2 mod-rm, [sib]
PSLLQregister, memory/register 0FF3 mod-rm, [sib]
PSLLWregister, memory/register 0FF1 mod-rm, [sib]
PSRADregister, memory/register 0FE2 mod-rm, [sib]
PSRAWregister, memory/register 0FE1 mod-rm, [sib]
PSRLDregister, memory/register 0FD2 mod-rm, [sib]
PSRLQregister, memory/register 0FD3 mod-rm, [sib]
PSRLWregister, memory/register 0FD1 mod-rm, [sib]
PSUBBregister, memory/register 0FF8 mod-rm, [sib]



Table C­1. IA MMX™ Instruction Set Mnemonics (Contd.)
MNEMONIC
OPERAND TYPES
Byte 1
Byte 2
Byte 3, [4]
PSUBDregister, memory/register 0FFA mod-rm, [sib]
PSUBSBregister, memory/register 0FE8 mod-rm, [sib]
PSUBSWregister, memory/register 0FE9 mod-rm, [sib]
PSUBUSBregister, memory/register 0FD8 mod-rm, [sib]
PSUBUSWregister, memory/register 0FD9 mod-rm, [sib]
PSUBWregister, memory/register 0FF9 mod-rm, [sib]
PUNPCKHBWregister, memory/register 0F68 mod-rm, [sib]
PUNPCKHDQregister, memory/register 0F6A mod-rm, [sib]
PUNPCKHWDregister, memory/register 0F69 mod-rm, [sib]
PUNPCKLBWregister, memory/register 0F60 mod-rm, [sib]
PUNPCKLDQregister, memory/register 0F62 mod-rm, [sib]
PUNPCKLWDregister, memory/register 0F61 mod-rm, [sib]
PXORregister, memory/register 0FEF mod-rm, [sib]

Notes:

* These are not the actual mnemonics:

PSHIMD represents the PSLLD, PSRAD and PSRLD instructions when shifting by immediate shift counts.

PSHIMW represents the PSLLW, PSRAW and PSRLW instructions when shifting by immediate shift counts.

PSHIMQ represents the PSLLQ and PSRLQ instructions when shifting by immediate shift counts.

The instructions that shift by immediate counts are differentiated by the ModR/M bytes (See Appendix B).


Trademark information