The CPUID instruction (opcode 0FA2) allows software to inquire about the CPU vendor, family, model, stepping, features, and cache information.
The presence of the CPUID instruction is indicated by the ability to change the value of the ID Flag (bit 21) in the EFLAGS register.
The CPUID level is determined by the value placed in the EAX register before the instruction is executed. Each CPUID level returns different information in EAX, EBX, ECX, and EDX registers.
Standard Levels
CPUID Instruction with EAX = 0000 0000h
Standard level 0h (EAX = 0) of the CPUID instruction returns the maximum standard CPUID levels supported as well as the processor vendor string.
After the instruction is executed, the EAX register contains the maximum standard CPUID levels supported. The maximum standard CPUID level is the highest acceptable value for the EAX register input. This does not include the extended CPUID levels. The EBX through EDX registers contain the vendor string of the processor. Note that the registers are placed out of order.
|
Register
|
Description
|
| EAX | Maximum Standard Levels |
| EBX-EDX-ECX | Vendor String - "CyrixInstead" |
|
Description
|
6x86(L)
|
M II*
|
MediaGX
|
MediaGX
MMX Enhanced
|
| Max Std Levels | 1 | 1 | 1 | 2 |
CPUID Instruction with EAX = 0000 0001h
Standard function 01h (EAX = 1) of the CPUID instruction returns the Processor Type, Family, Model, and Stepping information of the current processor in EAX. The EBX and ECX registers are reserved.
|
Register |
Description |
| EAX[3:0] | Stepping ID |
| EAX[7:4] | Model |
| EAX[11:8] | Family |
| EAX[15:12] | Type |
| EAX[31:16] | Reserved |
|
Description
|
6x86(L)
|
M II*
|
MediaGX
|
MediaGX
MMX Enhanced
|
| Stepping ID | xx | xx | xx | xx |
| Model | 2 | 0 | 4 | 4 |
| Family | 5 | 6 | 4 | 5 |
| Type | 0 | 0 | 0 | 0 |
The Standard Feature Flags supported are returned in the EDX register. Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features have protection control in CR4. Before using any of these features on the processor, the software should check the corresponding feature flag. Attempting to execute an unavailable feature can cause exceptions and unexpected behavior. For example, software must check bit 4 before attempting to use the Time Stamp Counter instruction.
|
Feature Flag |
EDX Bit |
CR4 Bit |
6x86 |
6x86(L) |
M II* |
MediaGX |
MediaGX
MMX Enhanced |
| FPU On-chip | 0 | - | x | x | x | x | x |
| Virtual Mode Extension | 1 | 0,1 | - | - | - | - | - |
| Debugging Extension | 2 | 3 | - | x | x | - | - |
| Page Size Extension | 3 | 4 | - | - | x | - | - |
| Time Stamp Counter | 4 | 2 | - | - | x | - | x |
| RDMSR / WRMSR Instructions | 5 | 8 | - | - | x | - | x |
| Physical Address Extension | 6 | 5 | - | - | - | - | - |
| Machine Check Exception | 7 | 6 | - | - | - | - | - |
| CMPXCHG8B Instruction | 8 | - | - | x | x | - | x |
| On-chip APIC Hardware | 9 | - | - | - | - | - | - |
| Undefined | 10 | - | - | - | - | - | - |
| SYSENTER / SYSEXIT Instructions | 11 | - |
- | - | - | - | - |
| Memory Type Range Registers | 12 | - | - | - | - | - | - |
| Page Global Enable | 13 | 7 | - | - | x | - | - |
| Machine Check Architecture | 14 | - | - | - | - | - | - |
| Conditional Move Instruction | 15 | - | - | - | x | - | x |
| Page Attribute Table | 16 | - | - | - | - | - | - |
| Undefined | 17-22 | - | - | - | - | - | - |
| MMX Instructions | 23 | - | - | - | x | - | x |
| Fast FPU Save and Restore | 24 | - | - | - | - | - | - |
| Undefined | 25-31 | - | - | - | - | - | - |
CPUID Instruction with EAX = 0000 0002h
Standard function 02h (EAX = 02h) of the CPUID instruction returns information that is specific to the Cyrix family of processors. Information about the TLB is returned in EAX. Information about the L1 Cache is returned in EDX. The EBX and ECX registers are reserved.
|
Register |
Description |
| EAX | TLB Information |
| EBX | Reserved |
| ECX | Reserved |
| EDX | L1 Cache Information |
|
Value |
Description |
| xxxx70xxh | TLB is 32 Entry, 4-way Set Associative, and has 4K Pages |
| xxxxxx01h | The CPUID instruction needs to be executed only once with an input value of 02h to retrieve complete information about the cache and TLB |
| xxxxxx80h | L1 Cache is 16K, 4-way Set Associative, and has 16 Bytes per Line |
|
Description |
MediaGX MMX Enhanced |
| EAX (TLB Info) | 00007001h |
| EDX (L1 Cache Info) | 00000080h |
