CPUID Instruction
The CPUID instruction (opcode 0FA2) allows software to inquire about the CPU vendor, family, model, stepping, features, and cache information.
The presence of the CPUID instruction is indicated by the ability to change the value of the ID Flag (bit 21) in the EFLAGS register.
The CPUID level is determined by the value placed in the EAX register before the instruction is executed. Each CPUID level returns different information in EAX, EBX, ECX, and EDX registers.
Standard Levels
CPUID Instruction with EAX = 0000 0000h
Standard level 0h (EAX = 0) of the CPUID instruction returns the maximum standard CPUID levels supported as well as the processor vendor string.
After the instruction is executed, the EAX register contains the maximum standard CPUID levels supported. The maximum standard CPUID level is the highest acceptable value for the EAX register input. This does not include the extended CPUID levels. The EBX through EDX registers contain the vendor string of the processor. Note that the registers are placed out of order.
|
Register
|
Description
|
| EAX | Maximum Standard Levels |
| EBX-EDX-ECX | Vendor String - "CyrixInstead" |
|
Description
|
6x86(L)
|
6x86MX
|
MediaGX
|
MediaGX
MMX Enhanced
|
| Max Std Levels | 1 | 1 | 1 | 2 |
CPUID Instruction with EAX = 0000 0001h
Standard function 01h (EAX = 1) of the CPUID instruction returns the Processor Type, Family, Model, and Stepping information of the current processor in EAX. The EBX and ECX registers are reserved.
|
Register |
Description |
| EAX[3:0] | Stepping ID |
| EAX[7:4] | Model |
| EAX[11:8] | Family |
| EAX[15:12] | Type |
| EAX[31:16] | Reserved |
|
Description
|
6x86(L)
|
6x86MX
|
MediaGX
|
MediaGX
MMX Enhanced
|
| Stepping ID | xx | xx | xx | xx |
| Model | 2 | 0 | 4 | 4 |
| Family | 5 | 6 | 4 | 5 |
| Type | 0 | 0 | 0 | 0 |
The Standard Feature Flags supported are returned in the EDX register. Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features have protection control in CR4. Before using any of these features on the processor, the software should check the corresponding feature flag. Attempting to execute an unavailable feature can cause exceptions and unexpected behavior. For example, software must check bit 4 before attempting to use the Time Stamp Counter instruction.
|
Feature Flag |
EDX Bit |
CR4 Bit |
6x86 |
6x86(L) |
6x86MX |
MediaGX |
MediaGX
MMX Enhanced |
| FPU On-chip | 0 | - | x | x | x | x | x |
| Virtual Mode Extension | 1 | 0,1 | - | - | - | - | - |
| Debugging Extension | 2 | 3 | - | x | x | - | - |
| Page Size Extension | 3 | 4 | - | - | x | - | - |
| Time Stamp Counter | 4 | 2 | - | - | x | - | x |
| RDMSR / WRMSR Instructions | 5 | 8 | - | - | x | - | x |
| Physical Address Extension | 6 | 5 | - | - | - | - | - |
| Machine Check Exception | 7 | 6 | - | - | - | - | - |
| CMPXCHG8B Instruction | 8 | - | - | x | x | - | x |
| On-chip APIC Hardware | 9 | - | - | - | - | - | - |
| Undefined | 10 | - | - | - | - | - | - |
| SYSENTER / SYSEXIT Instructions | 11 | - |
- | - | - | - | - |
| Memory Type Range Registers | 12 | - | - | - | - | - | - |
| Page Global Enable | 13 | 7 | - | - | x | - | - |
| Machine Check Architecture | 14 | - | - | - | - | - | - |
| Conditional Move Instruction | 15 | - | - | - | x | - | x |
| Page Attribute Table | 16 | - | - | - | - | - | - |
| Undefined | 17-22 | - | - | - | - | - | - |
| MMX Instructions | 23 | - | - | - | x | - | x |
| Fast FPU Save and Restore | 24 | - | - | - | - | - | - |
| Undefined | 25-31 | - | - | - | - | - | - |
CPUID Instruction with EAX = 0000 0002h
Standard function 02h (EAX = 02h) of the CPUID instruction returns information that is specific to the Cyrix family of processors. Information about the TLB is returned in EAX. Information about the L1 Cache is returned in EDX. The EBX and ECX registers are reserved.
|
Register |
Description |
| EAX | TLB Information |
| EBX | Reserved |
| ECX | Reserved |
| EDX | L1 Cache Information |
|
Value |
Description |
| xxxx70xxh | TLB is 32 Entry, 4-way Set Associative, and has 4K Pages |
| xxxxxx01h | The CPUID instruction needs to be executed only once with an input value of 02h to retrieve complete information about the cache and TLB |
| xxxxxx80h | L1 Cache is 16K, 4-way Set Associative, and has 16 Bytes per Line |
|
Description |
MediaGX MMX Enhanced |
| EAX (TLB Info) | 00007001h |
| EDX (L1 Cache Info) | 00000080h |
Extended Levels
Extended CPUID Level support testing consists of executing a CPUID instruction with the EAX register initialized to 8000 0000h and testing the return value in EAX. If a value greater than or equal to 8000 0000h is returned to the EAX register by the CPUID instruction, the processor supports extended CPUID Levels.
CPUID Instruction with EAX = 8000 0000h
Extended function 8000 0000h (EAX = 80000000h) of the CPUID instruction returns the maximum extended CPUID levels supported by the current processor in EAX. The other registers are reserved.
|
Register |
Description |
| EAX | Maximum Standard Levels |
| EBX-ECX-EDX | Reserved |
|
Description |
MediaGX
MMX Enhanced |
| Max Extended Levels | 80000005h |
CPUID Instruction with EAX = 8000 0001h
Extended function 8000 0001h (EAX = 80000001h) of the CPUID instruction returns the Processor Type, Family, Model, and Stepping information of the current processor in EAX. The EBX and ECX registers are reserved.
|
Register |
Description |
| EAX[3:0] | Stepping ID |
| EAX[7:4] | Model |
| EAX[11:8] | Family |
| EAX[15:12] | Type |
| EAX[31:16] | Reserved |
|
Description
|
MediaGX
MMX Enhanced
|
| Stepping ID | xx |
| Model | 4 |
| Family | 5 |
| Type | 0 |
The Extended Feature Flags supported are returned in the EDX register. Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features have protection control in CR4. Before using any of these features on the processor, the software should check the corresponding feature flag.
|
Feature Flag |
EDX Bit |
CR4 Bit |
MediaGX
MMX Enhanced |
| FPU On-chip | 0 | - | x |
| Virtual Mode Extension | 1 | 0,1 | - |
| Debugging Extension | 2 | 3 | - |
| Page Size Extension | 3 | 4 | - |
| Time Stamp Counter | 4 | 2 | x |
| Cyrix Model-Specific Registers | 5 | 8 | x |
| Undefined | 6 | - | - |
| Machine Check Exception | 7 | 6 | - |
| CMPXCHG8B Instruction | 8 | - | x |
| Undefined | 9 | - | - |
| Undefined | 10 | - | - |
| SYSCALL / SYSRET Instructions | 11 | - | - |
| Undefined | 12 | - | - |
| Page Global Enable | 13 | 7 | - |
| Undefined | 14 | - | - |
| Integer Cond. Move Instruction | 15 | - | x |
| FPU Cond. Move Instruction | 16 | - | - |
| Undefined | 17-22 | - | - |
| MMX Instructions | 23 | - | x |
| 6x86MX Multimedia Extensions | 24 | - | - |
| Undefined | 25-31 | - | - |
CPUID Instruction with EAX = 8000 0002h - 8000 0004h
Extended function 8000 0002h through 8000 0004 (EAX = 80000002h, 80000003h, 80000004h) of the CPUID instruction returns an ASCII string containing the name of the current processor. These functions eliminate the need to look up the processor name in a lookup table. Software can simply call these functions to obtain the name of the processor. The string may be 48 ASCII characters long, and is returned in little endian format. If the name is shorter than 48 characters long, the remaining bytes will be filled with ASCII NULL character (00h).
|
8000 0002h |
8000 0003h |
8000 0004h |
| EAX | CPU Name 1 | EAX | CPU Name 5 | EAX | CPU Name 9 |
| EBX | CPU Name 2 | EBX | CPU Name 6 | EBX | CPU Name 10 |
| ECX | CPU Name 3 | ECX | CPU Name 7 | ECX | CPU Name 11 |
| EDX | CPU Name 4 | EDX | CPU Name 8 | EDX | CPU Name 12 |
CPUID Instruction with EAX = 8000 0005h
Extended function 8000 0005h (EAX = 80000005h) of the CPUID instruction returns information about the TLB and L1 Cache to be looked up in a lookup table.
|
Register |
Description |
| EAX | Reserved |
| EBX | TLB Information |
| ECX | L1 Cache Information |
| EDX | Reserved |
|
Value |
Description |
| xxxx70xxh | TLB is 32 Entry, 4-way Set Associative, and has 4K Pages |
| xxxxxx01h | The CPUID instruction needs to be executed only once with an input value of 02h to retrieve complete information about the cache and TLB |
| xxxxxx80h | L1 Cache is 16K, 4-way Set Associative, and has 16 Bytes per Line |
|
Description |
MediaGX MMX Enhanced |
| EBX (TLB Info) | 00007001h |
| ECX (L1 Cache Info) | 00000080h |