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Developer Frequently Asked Questions
- Q. Does 6x86 support
CPUID?
- A. Yes, but it is
normally turned off in the BIOS.
-
- Q. Does the 6x86MX
support CPUID?
- A. Yes. For more
information, see the databook, or
Cyrix CPU Detection Guide.
-
- Q. Does the 6x86MX
have RDTSC?
- A. Yes. For more
information, see the databook, or
Cyrix CPU Detection Guide.
-
- Q. What
new features are in a 6x86L CPU?
- A. Debug Extensions
(I/O Breakpoints), Compare Exchange Eight Byte (CMPEX8B)
-
- Q. How
do I detect a 6x86, 6x86MX, or MediaGX?
- A. Refer to
Cyrix CPU Detection Guide.
-
- Q. Does
the MediaGX support CPUID?
- A. The current
version of the MediaGX does not. The future version will
support CPUID and RDTSC.
-
- Q. Can
I optimize for the 6x86 and 6x86MX?
- A. Very little. There
are no pairing rules, and most dependencies are removed.
See Application Note 106 for more information.
-
- Q. What
are the pairing rules for the 6x86 and 6x86MX?
- A. There are none.
-
- Q. How
do I figure out the correct MHz?
- A. See
BIOS Writer's Guide. (PDF 264K)
-
- Q. What
is the "PR Rating" and how can it be
determined?
- A. It is a
Performance Rating for comparing different vendors CPUs
based on Ziff-Davis Winstone benchmark. (See
also). It may be determined by a lookup table.
-
- Q. What
is the difference between the 6x86 and 6x86MX?
- A. See Below:
-
Summary
of Differences Between the
6x86 and 6x86MX CPUs
| Feature |
6x86 |
6x86MX |
| Pinout |
P54C (socket 7) |
P55C (socket 7) |
| Supply Voltage |
6x86 3.3V or 3.52V
6x86L 2.8V core; 3.3V I/O |
2.9V core; 3.3V I/O |
| CPU Primary Cache |
16K Size 4-way 512 lines 32 bytes per line |
64K Size 4-way 2048 lines 32 bytes per line |
| TLB |
L1: 128 entry / Victim TLB: 8 entry |
L1: 16 entry / L2: 384 entry |
| BTB |
256 |
512 |
| Lockable Cache |
no |
yes |
| Time Stamp Counter |
no |
yes |
| Performance Counters |
no |
yes |
| Global PTE |
no |
yes |
| CPUID enabled |
no |
yes |
| MMX |
no |
yes |
| 6x86MX Multimedia Extensions |
no |
yes |
| Nestable SMI support |
no |
yes |
| CMOV |
no |
yes |
| Cacheable SMI Code/Data |
no |
yes |
- Q. What
compiler optimizations should I use?
- A. Do not use Pentium
compiler optimizations since that leads to larger code.
-
- Q. Do
the 6x86 and 6x86MX processors support MMX instructions?
- A. The 6x86MX
supports the MMX instructions and includes additional multimedia instructions. See Application Note 106.
-
- Q. How do I check for MMX support?
- A. Do CPUID (eax=1)
and check the feature flags bit 23 for MMX support. See
Cyrix CPU Detection Guide
- Q. What is this new XCHG Errata
I'm hearing about? Is it a bug?
- A.
An issue has been reported by Aleksandr K. Konosevich, of ESHS Lab with the
6x86 core that appears to be confined to one piece of developmental
software. The problem will cause a system to lock up due to interrupts not
being serviced. The problem is easily detectable by the CPU freezing up. To get perspective
on this issue, millions of 6x86 core products have been shipped over the last 3 years and
this is the first report of the problem.
The problem is with the following code:
top: xchg [bx], ax
mov ax, cx
jmp top
The fix to the above code is to add a NOP after the xchg:
top: xchg [bx], ax
nop
mov ax, cx
jmp top
The issue can be remedied with an opcode matching capability that is unique to Cyrix 6x86 core
products. The pipexchg.zip utility can be placed in the Autoexec.bat in DOS/Win9x and the problem
will not occur.
- Q. What is the 'Intel F0 Bug'
and do Cyrix processors have this bug?
- A.
The Intel family of Pentium processors do not properly handle the following code sequence:
(Assembly Program)
.MODEL small
.386
.CODE
.STARTUP
db 0f0h ; LOCK
db 00fh, 0c7h, 0c8h ; CMPEXG8B EAX
.EXIT ; exit to DOS
END
The CMPEXG8B EAX is an invalid instruction, and should generate an 'invalid exception'.
Intel Pentium processors do not seem to handle this properly and lock up the system.
All the Cyrix family of processors handle the code sequence properly.
Last update: 13-Nov-97
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