See the latest FAQ addition.
Feature | M2 Processor | 6x86 Processor |
---|---|---|
Pinout | P55C | P54C |
Supply Voltage | 2.8V Core; 3.3V I/O | 6x86: 3.3V or 3.52V; 6x86L: 2.8V core; 3.3V I/O |
CPU Primary Cache | 64-KByte | 16-KByte |
TLB | L1: 16 entry; L2: 384 entry | L1: 128 entry; Victim TLB: 8 entry |
Branch Prediction | 512 entry branch target cache; 1024 entry branch history table | 256 entry branch target cache; 512 entry branch history table |
MMX Instructions | Yes | No |
Performance Monitor including Time Stamp Counter and Model Specific Registers | Yes | No |
Scratchpad RAM in Primary Cache | Yes | No |
Cacheable SMI Code/Data | Yes | No |
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