i960® JF Microprocessor Highlights i960 processor compatible RISC core 31 VAX MIPS execution at 33 MHz 4-Kbyte two-way set associative instruction cache 2-Kbyte direct mapped data cache 1-Kbyte on-chip data RAM Built-in interrupt controller i960 KA processor compatible external bus and i960 CA processor compatible programmable bus width support Two 32-bit timers Refer to i960 Jx processor product brief, order number 272506, for more information I/O Interfaces - Why Add Intelligence? Intelligent I/O systems offer superior server performance possibilities in the two basic areas of server I/O -- network and storage. In network I/O, the bridge and routing functions can be integrated into the servers. Ethernet or token ring LAN interfaces with intelligent I/O, which handles the frequent I/O interrupts and intelligently buffers messages to and from the host. This allows the host to streamline applicants processing and to use other system resources, such as the system bus and memory, more effectively. In WAN interfaces, intelligent I/O processing also offers the potential for significant performance improvements. For example, intelligent WAN interfaces can compress large message files before transmission, freeing the host CPU to perform more valuable application tasks and allowing more users to share the same fixed, wide-area connection. Additionally, the host CPU is transparent to this operation, so it's a more efficient use of the WAN. In RAID controllers, the server can initiate a disk store or retrieve command as if it were writing to a single disk. The intelligent RAID controller separates commands into parallel read or write commands to its attached array of disks. This parallel operation, controlled by the intelligent I/O processor, compensates for the single-disk spin-up delay, protecting the data. The result is superior data transfer rates as well as greater reliability, a critical issue as servers become more widely used for corporate computing and database creation. Another example of how intelligent I/O improves server storage is in caching disk controllers. The host can write a data file to the intelligent disk controller cache at speeds matching the fast DRAM memory. The host application execution continues while the I/O processor controls the actual disk storage sequences. Expanding Server Capabilities The PCI local bus standard increases the maximum number of electrical loads connected to the local PCI local bus. This drives the requirements for PCI-to-PCI bridges within the server to expand the number of card slots. Today' s servers support up to three PCI card slots. Additional card slots require a PCI-to-PCI bridge to create a hierarchy of electrically isolated PCI buses. The i960 RP processor provides the functionality to increase the number of server expansion card slots and to create an intelligent I/O subsystem. Expanding The Market By Reducing System Costs Because the PCI bus features allow for greater concurrency, each I/O processor's MIPS delivers a greater contribution to overall system performance. The low-cost i960 RP processor uses peripheral components to provide the new physical interface to I/O devices. Local bus standardization helps migrate the peripheral components, providing them with direct connection to the PCI bus. When combined with an embedded I/O processor, the result is an intelligent I/O subsystem. Intelligent I/O Processor Requirements Bus Bandwidth Maximize Bus-Throughput & Concurrency Reduce wait-states PCI Availability Isolating Data Traffic Processing Performance Reduce interrupts to Host CPU Handle I/O processing Data Integrity Notification to I/O Processor Flexibility Create cost effective, performance driven, memory systems

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supercedes previously published specifications on these devices from Intel. *Other brands and names are the property of their respective owners.

* Legal Information © 1999 Intel Corporation