8XC152 Interframe Space 8XC152 Requires Interframe Space in SDLC 8XC152 Requires Interframe Space in SDLC The following is an explanation of how to minimize the effects of the interframe space while in SDLC mode. Further explanation of the interframe space is in section 3.2.3 of the 1994 83C152 Hardware Description Manual. The interframe space is a period of time that all stations are prevented from transmitting after any activity on the serial communication link is detected. The purpose of this waiting period is to give time for a receiver to recover from a previously received frame. The reason for implementing this change was to better support ISDN applications. For those users that do not want to use the interframe space in SDLC mode, the best they can do is to minimize its impact by programming the special function register, IFS, with 02. IFS can only be loaded with even numbers, so 1 cannot be used. After a reset, IFS defaults to 00H which translates into a 256 bit time interframe space. Loading IFS with 02 will prevent a transmission from starting until two bit times after an idle condition on the serial link is detected. An idle condition is defined as a constant 1 on the link for 15 bit times when SDLC mode is selected. C152 users that have implemented the external GSC clock option on the C152 must be informed that at least 17 clocks must occur after any activity on the link before the next transmission will begin. If an external clock cannot fulfill these requirements, a work-around must be implemented. One way to do this is to switch to the internal baud rate generator after any link activity. The internal clock must be enabled for at least 18 bit times before switching back to external clock mode.

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