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12-9-93
The EPA's input-capture structure basically consists of a time buffer (EPAx buffer or "EPAx_BUF") and a time register (EPAx_TIME) as shown in the following diagram. Assume that both the EPAx buffer and EPAx_TIME are empty and an event occurs at the pin. After the event is recognized as valid, the current TIMERx count value will be loaded through the EPAx buffer into EPAx_TIME. The act of data moving from EPAx_BUF to EPAx_TIME is what causes the actual EPA interrupt. When a second event occurs at the pin, the current TIMERx value will be loaded into the EPAx buffer and held there until the user reads EPAx_TIME. A third event would be considered an overrun since both the time and buffer registers are full. If the ON/RT bit in the EPAx_CONTROL register is a "0", this third event will be ignored. If the ON/RT bit is a "1", this third event time will overwrite the second event time in the EPAx buffer. Either way, an overrun interrupt will be generated. When the user reads EPAx_TIME, the contents of the EPAx buffer will automatically be transferred into EPAx_TIME and an EPA interrupt will occur.
When an event occurs on the associated port pin, the following sequence of events occur:
1. Event occurs at the associated EPA pin.
2. If enabled by the user, the edge detection circuitry will generate a "edge valid" signal when the specified edge is detected.
3. The "edge valid" signal is gated by both the ON/RT bit of the EPAx_CONTROL register and an "overrun" signal. The "overrun" signal flags that both the EPAx buffer and EPAx_TIME are full and that an overrun condition will occur. One of four scenarios will take place at this point:
ON/RT buffer/time reg's status Action taken when a valid edge occurs 0 empty edge is captured and loaded into buffer/time register. 0 full new data ignored - no capture, EPA int. or transfer; OVR_INT interrupt occurs. 1 empty edge is captured and loaded into buffer/time register. 1 full old data is overwritten in the EPAx buffer, OVR_INT interrupt occurs.
4. The "edge valid" signal is used to generate a "capture timer" signal and an "event interrupt / transfer" signal.
EPA "lock-up" occurs when an input signal with a frequency high enough to cause overruns is present on an enabled EPA pin and the ON/RT bit is set ("1" = old data overwritten on overrun) and a read of EPAx_TIME is performed at the exact instant the captured edge is recognized as valid by the EPA. The input frequency that this occurs at is dependent upon the length of the user's interrupt service routine as well as other factors. "Lock-up" is a generic term used to define the case where subsequent edges input on an EPA pin are not recognized by the EPA peripheral. During "lock-up" both the EPAx_TIME register and the EPAx time buffer are full without a pending interrupt to signal that a read of EPAx_TIME is necessary. Once in this condition, and without the user's code accounting for overruns, the particular EPA channel will stay "locked-up" until reset is asserted.
The particular EPA channel will recover from the lock-up condition if the EPAx_TIME register is read. The act of reading EPAx_TIME allows the buffered time value to be moved into EPAx_TIME. This clears the buffer and allows another event to be captured. Remember that the act of the buffer contents being transferred to the EPAx_TIME register is what actually generates the EPAx interrupt.
Any one of the following suggestions can be used to prevent your system from experiencing the EPA "lock-up" scenario.
1) Set ON/RT to "0":
This method does not consider the captured edge until the EPAx_TIME register is read and the data in the buffer is transferred to EPAx_TIME.
This will prevent the "lock-up" behavior by ignoring new input capture events when both the EPAx buffer and EPAx_TIME contain valid capture times. Since the ON/RT bit gates the "edge valid" signal, the "capture timer" and "event interrupt / transfer" signals are never generated, thus preventing the "lock-up" scenario from occuring.
The "edge valid" signal will still be active to indicate an overrun occurred. The OVR_INT pending bit in EPA_PEND is set along with the EPA_INTx bit in the INT_PEND register. At the same time, the transfer of EPAx buffer data to EPAx_TIME will occur and generate another EPAx interrupt. This means the lock-up mode never has the opportunity to occur. In this situation the OVR_INT will always be pending/waiting until the EPAx interrupts are serviced because the EPA_INT has higher priority all the time.
2) Enable the OVR_INTx in the user code and read the EPAx_TIME register within the ISR:
This is more of a reactive method of resolving the "lock-up" situation as opposed to proactively preventing it. Using this method, the programmer handles overruns within his/her OVR_INTx ISR (interrupt service routine) in a way that is acceptable for their particular application. When lock-up occurs, EPAx interrupts will be locked-up but the OVERRUN signal will be generated to set the pending bits in the EPA_PEND register. The OVR_INT interrupt will then be acknowledged and its interrupt service routine will read out the EPAx_TIME. The read of EPAx_TIME will generate an EPAx pending interrupt and will clear the overrun condition. This will cause the device to come out of the lock-up mode.
3) Check for pending EPAx interrupts prior to exiting an EPAx ISR.
Another method for avoiding a possible "lock-up" scenario is to check for pending EPAx interrupts prior to exiting an EPAx ISR. This is an easy way to detect overruns and additional interrupts. It can also save loop time by eliminating the latency necessary to service the pending interrupt. This method cannot be used with the Peripheral Transaction Server (PTS) since the user cannot service additional interrupts during a PTS cycle. If the PTS is being used, one of the other methods should be used.
The EPA "lock-up" issue can occur when events occur at an EPA input pin faster than a given EPAx ISR can process them and no methodology is in place to address the overruns. Three solutions are given above to deal with EPA input overruns. If EPA overruns are possible, it is important that OVR_INTs be enabled to address the overrun or the overruns should be ignored (ON/RT="0"). Regardless of the method used for preventing EPA "lock-up", it is important to comprehend the maximum input frequencies one may encounter in a given application as well as the ISR execution time.
* Legal Information © 1999 Intel Corporation