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MCS(R) 96: Interfacing BookBlock Flash Memories to the MCS 96 Family

(#2329) MCS(R) 96: Interfacing BookBlock Flash Memories to the MCS 96 Family

MCS® 96: Interfacing BookBlock Flash Memories to the MCS 96 Family


This article reviews Intel® BootBlock flash memory interfaces to MCS® 96 embedded processors. Three specific examples will illustrate various techniques and options available to the system designer. The article will also discuss general recommendations for all MCS 96/flash designs.

Intel's MCS 96 products, in conjunction with the BootBlock flash memory family, provide a powerful processor/memory combination for today's embedded control designs. MCS 96 devices are high-performance 16-bit microcontrollers with integrated memory and peripherals, including ports, timers, pulse width modulators and A/D converters. They easily handle high speed calculations and fast input/output operations.

Flash memory brings easy update ability to designs that in the past might have used ROM or EPROM for system code storage. Unlike battery-backed SRAM, flash memory is fully nonvolatile. Flash memory has demonstrated orders of magnitude better reliability, and much higher density, than EEPROM. Flash memory, with its much simler cell structure, is also cheaper on a cost-per-bit basis than either SRAM or EEPROM.

BootBlock flash memory products have been specifically defined for the requirements of embedded control code storage. Features of these devices include:


This design example interfaces the 28F001BX-B120 to the 80C198-16. The 80C198-16 is a 16 MHz member of the MCS 96 family, with an 8-bit external data bus and an integrated A/D converter. The 28F001BX-B120 is a 120ns tACC version of the 128 KByte x8 BootBlock flash memory family, with the boot block located at the bottom of the memory map (see Figure 1). A system diagram is shown in figure 2, with a corresponding system memory map in figure 3. This example highlights the following design techniques:

Higher-Order Address Generation

Most members of the MCS 96 family are address pin-constrained to a 64 KByte memory map. To access the 128 KByte 28F001BX, plus any other external memory/peripheral devices, upper addresses are generated using the programmable logic device U4 as shown in Figures 2 and 3. Flash memory addresses A16-15 powerup and reset to "0"s, and are changed by writing the desired value to an internal two-bit "register" within the EPLD, using data bits D1-0. An alternate source of upper address bits is the High Speed Outputs (HS03-0) of the 80C198, if not used elsewhere in the design. As shown in Figure 3, 80C198 register, port and interrupt vector location are common to all "pages".

Figure 1. 28F001BX-B Device Memory Map

Figure 2. 80C198/28F001BX-B System Interface

Flash Memory Address Inversion

The 28F001BX boot blcok is intended to store core unchanging system initialization code, port pin "page control" software and the flash memory program/erase algorithms. On the 28F001BX-B,it is located at device addresses 0000h-1FFFh (see Figure 1). Inverting address A13 with component U4 alters the 29F001BX-B memory map as it appears to the 80C198, as shown in Figure 4. This "moves" the boot block to addresses 2000h-3FFFh, compatible with the 80C198 boot/reset address of 2080h. Software developers take note: this approach also "movees" 8 KByte main block segments.

External SRAM

Component U3 is a 2Kx8 SRAM, with the following uses:

For the latter two uses, the software must be executed external to the flash memory, either to change flash memory "pages" or to update flash memory contents. Therefore, the SRAM must be commonly located in every 64 KByte memory "page". The logic of component U4 that generates CE for the SRAM, being independent of the state of 28F001BX "addresses" A15 and A16, ensures this (see Figure 3).

The code that executes port pin "page control" and flash memory update software is stored in the 28F001BX boot block, and is copied to the external SRAM. A "JUMP" to the SRAM memory address begins execution.

Miscellaneous Details

Latch U5 latches address A7-0 for use by the 28F001BX and SRAM. Buffer U6 eliminates bus contention as the SRAM is selected and the 28F001BX is deselected, due to the fast data bus "enable" of the SRAM compared to the bus "release" delay of the flash memory.

Table 1 details the external memory timings of the 80C198-16 (along with the external logic shown) at various wait states, and the corresponding timings of the 28F001BX-B120. As can be seen, this is a 1 wait state design.

Figure 3. 80C198/28F001BX-B System Memory Map

Figure 4. 28F001BX-B Memory Map
(as it appears to the system aster A13 address inversion)

If a higher density flash memory is needed in this x8 design, the 256 KByte 28F002BX or 512 KByte 28F004BX can be used. Both of these devices offer 60ns speed bins, for high-performance no-wait-state read access.

Specifications80C198-16/Logic Timings (0 WS)80C198-16/Logic Timings (1 WS)28F001BX-B120 TimingsUnit
ACC to Output DelY)110.5235.5120ns
CE(Chip Enable to Output)110.5235.5120ns
OE Enable to Output)32.5157.550ns
ELL Enable Setup to Write Enable Going Low)9021510ins
WLWH Enable Pulse Width)47.5172.550ins
AVWH Setup to Write Enable Going High)137.5262.550ins
DVWH Setup to Write enable Going High)32.5157.550ins
WHDX Hold from Write Enable High)101010ins
WHAX Hold from Write Enable High)32.532.510ins
WHEH Enable Hold from Write Enable High)32.532.510ins

Table 1. Timing Analysis for 80C198-16/28F001BX-B120 Design (See Figure 2)


The 80C196KR product family consists of four devices (80C196KR, 80C196KQ, 80C196JQ and 80C196JQ) that differ in the size of SRAM and the number of integrated peripheral devices. They all communicate with external memory and logic through a 16-bit external data bus. If the 80C196KR family is used for the embedded processor, interface to flash memory is much simpler than in the earlier 80C198 example.

These microcontrollers integrate not only data SRAM but also code SRAM on-chip, in 128 or 256 byte densities. This code SRAM size is sufficient to store "page control" and flash update software. Therefore, external SRAM is only needed if internal data SRAM size is insufficient for the given application.

The 28F200BX or 28F400BX are the recommended BootBlock flash memory devices for the 80C196KR family. These flash memories both have x16 data bus interfaces, and their 60ns read speeds enable high-performance no-wait-state access. Both the 28F200BX and 28F400BX (see Figure 5 and 6) integrate 16 KByte boot blocks located at device addresses 0000h-3FFFh. This overlaps the MCS96 2080h boot address, so no address "swapping" to relocate the boot block is required.

The 80C196KR family, like the 80C198, is address pin-constrained to a 64 KByte memory map. As in the 80C198 design example earlier, alternate means are used to "construct" upper system address bits and access the full density of the 28F200BX or 28F400BX. In this case, the port 1 outputs, if available, provide a straightforward means of implementing upper address bits. Since they power up and reset to "1"s, the port pins are inverted, as shown in Figure 7, to allow system boot from page "0" (see Figure 3).

The newly-introduced 8xC196NT and 8xC196NQ are upgraded versions of the 80C196KR. They retain the 80C196KR integrated code SRAM, and in addition include additional address pins. This raises the amount of directly-accessed external memory from 64KBytes to 1MByte, more than sufficient to handle the density of Intel's BootBlock flash memory devices. System address reconstruction using port pins is not needed in 8xC196NT family designs. Again, the recommended flash memories for these designs are the 28F200BX and 28F400BX.


The following tips are common design techniques for all MCS 96 microcontroller designs.

Figure 5. 28F200BX-B Device Memory Map

Redirection of Interrupt Vectors

The design example and overviews described earlier all map the common MCS 96 boot location of 2080h to the boot block of the appropriate BootBlock flash memory. The boot block is hardware-lockable via the flash memory PWD input, and code in the boot block is not normally in-system updated. The boot block also stores the lower and upper interrupt vector tables, at system addresses 2000h-2013h and 2030h-203Fh, respectively. As flash memory system code is updated, the starting address locations of interrupt service routines correspondingly change. To encompass this change, point the primarily interrupt vector table locations (in the boot block) to a secondary interrupt vector table at a fixed location in an updateable main or parameter block. As the system code is updated, this secondary vector table is also updated to reflect the new interrupt routine starting address locations.

Figure 6. 28F400BX-B Device Memory Map

12V Converters

Intel flash memory devices require 12V + 5% for byte program and block erase. Where a voltage supply with these specifications is not already available to service other components of the system, a broad range of 12V converters is available that translate existing power supply voltages (higher or lower) to meet flash memory requirements. These converters have been optimized around one or several of the following key parameters:

Application note AP-357 "Power Supply Solutions for Flash Memory" (order number #292092) compares a wide range of 12V solutions against the above parameters. It is available from your local Intel distributor sales office. The following vendors are representatives of those offering 12V converters.

Linear Technology Corporation
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
(408) 432-1900

Maxim Integrated Products
120 San Gabriel Drive
Sunnyvale, CA 94086
(408) 737-7600

Motorola Semiconductor Inc.
616 West 24th St.
Tempe, AZ 85282
(800) 521-6274

National Semiconductor
2900 Semiconductor Dr.
P.O. Box 58090
Santa Clara, CA 95052
(408) 721-5000

Figure 7. High-Order Flash Memory Address Generation Using MCS 96 Port Pins

PWD Control

The PWD input in BootBlock devices has several functions:

The design example shown in Figure 2 gates the BootBlock PWD input with a system RESET generated by any external RESET input (if present), and by the ouput the MAX705 (U7). The MAX705 is a VCC monitoring circuit available from Maxim Integrated Products, and is representative of comparable offerings by several semiconductor vendors. If power consumption is a concern in the end design, the PWD input can be further gated by a MCS 96 port pin, to access Deep Powerdown mode. Since the boot block is typically soldered on the system board, no provision for 12V on the PWD input is shown in Figure 2. A hardware jumper is one way of accomplishing this, if required.

For more information on the products or concepts discussed in this article, please contact your local Intel distributor sales office.

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