This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as DRAM and the external cache. It also coordinates communications between the conventional ISA bus and the PCI bus. It must be stated that these items should never need to be altered. The default settings have been chosen because they provide the best operating conditions for your system. The only time you might consider making any changes would be if you discovered that data was being lost while using your system.
The first chipset settings deal with CPU access to dynamic random access memory (DRAM). The default timings have been carefully chosen and should only be altered if data is being lost. Such a scenario might well occur if your system had mixed speed DRAM chips installed so that greater delays may be required to preserve the integrity of the data held in the slower memory chips.
DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data lost.
3 Three clocks. 4 Four clocks.
Four clocks is the default.
This sets the number of CPU clocks allowed before reads and writes to DRAM are performed.
8/7 Eight clocks leadoff for reads and seven clocks leadoff for writes. 7/5 Seven clocks leadoff for reads and five clocks leadoff for writes.
8/7 Leadoff timing is the default.
When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from Row Address Strobe (RAS) to Column Address Strobe (CAS).
3 Three CPU clock delay. 2 Two CPU clock delay.
3 CPU clocks is the default.
This sets the timing for burst mode reads from DRAM. Burst read and write requests are generated by the CPU in four separate parts. The first part provides the location within the DRAM where the read or write is to take place while the remaining three parts provide the actual data. The lower the timing numbers, the faster the system will address memory.
x2222 Read DRAM timings are 2-2-2-2 x3333 Read DRAM timings are 3-3-3-3 x4444 Read DRAM timings are 4-4-4-4
x2222 timings is the default.
The Triton II chipset is capable of allowing a DRAM read request to be generated slightly before the address has been fully decoded. This can reduce all read latencies.
More simply, the CPU will issue a read request and included with this request is the place (address) in memory where the desired data is to be found. This request is received by the DRAM controller. When the 'Speculative Leadoff' is enabled, the controller will issue the read command slightly before it has finished determining the address.
Disabled is the default.
When this is enabled, the chipset will insert one extra clock to the turn-around of back-to-back DRAM cycles.
Disabled is the default.
When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached, provided that the cache controller is enabled.
Enabled BIOS access cached Disabled BIOS access not cached
Disabled is the default.
As with caching the System BIOS above, enabling the Video BIOS cache will cause access to video BIOS addressed at C0000H to C7FFFH to be cached, if the cache controller is also enabled,
Enabled Video BIOS access cached Disabled Video BIOS access not cached
Disabled is the default.
The recovery time is the length of time, measured in CPU clocks, which the system will delay after the completion of an input/output request. This delay takes place because the CPU is operating so much faster than the input/output bus that the CPU must be delayed to allow for the completion of the I/O.
This item allows you to determine the recovery time allowed for 8 bit I/O. Choices are from 1 to 8 CPU clocks.
1 clock is the default.
This item allows you to determine the recovery time allowed for 16 bit I/O. Choices are from 1 to 4 CPU clocks.
1 clock is the default.
In order to improve performance, certain space in memory can be reserved for ISA cards. This memory must be mapped into the memory space below 16 MB.
Enabled Memory hole supported. Disabled Memory hole not supported.
Disabled is the default.
This allows your hard disk controller to use the fast block mode to transfer data to and from your hard disk drive (HDD).
Enabled IDE controller uses block mode Disabled IDE controller uses standard mode.
Enabled is the default.
Enabling 32-bit transfer mode allows faster access to data on your hard disk drive.
Enabled 32-bit transfer mode used. Disabled Conventional transfer mode used.
Enabled is the default.
IDE hard drive controllers can support up to two separate hard drives. These drives have a master/slave relationship which are determined by the cabling configuration used to attach them to the controller. Your system supports two IDE controllers--a primary and a secondary--so you have to ability to install up to four separate hard disks.
PIO means Programmed Input/Output. Rather than have the BIOS issue a series of commands to effect a transfer to or from the disk drive, PIO allows the BIOS to tell the controller what it wants and then let the controller and the CPU perform the complete task by themselves. This simpler and more efficient (and faster).
Your system supports five modes, numbered from 0 (default) to 4, which primarily differ in timing. When Auto is selected, the BIOS will select the best available mode. This is true for the next four setup items:
As stated above, your system includes two built-in IDE controllers, both of which operate on the PCI bus. This setup item allows you either to enable or disable the primary controller. You might choose to disable the controller if you were to add a higher performance or specialized controller.
Enabled Primary HDD controller used -- Default Disabled Primary HDD controller not used.
As above for the Primary controller, this setup item you either to enable or disable the secondary controller. You might choose to disable the controller if you were to add a higher performance or specialized controller.
Enabled Primary HDD controller used Disabled Primary HDD controller not used.
Enabled is the default.
This item allows you designate an IDE controller board inserted into one of the physical PCI slots as your secondary IDE controller.
Enabled External IDE controller designated as the secondary controller Disabled No IDE controller occupying a PCI slot.
Disabled is the default.
Peer concurrancy means that more than one PCI device can be active at a time.
Enabled Multiple PCI devices can be active. Disabled Only one PCI device can be active at a time.
Enabled is the default.
When disabled, the chipset behaves as if it were the earlier Triton chipset.
This item allows you to select between two methods of DRAM error checking, ECC and Parity (default).
This should be enabled if your system has a floppy disk controller (FDC) installed on the system board and you wish to use it. Even when so equipped, if you add a higher performance controller, you will need to disable this feature.
Enabled Onboard floppy disk controller active (Default) Disabled Either onboard floppy disk controller absent of not to be used.
This allows you to determine how the serial port number one installed on your motherboard is to be configured.
COM1, 3F8 IRQ 4 (Default) COM2, 2F8 IRQ 3 COM3, 2E8 IRQ 3 COM4, 3E8 IRQ 4 Disabled Serial port 1 disabled
This allows you to determine how the serial port number two installed on your motherboard is to be configured.
COM1, 3F8 IRQ 4(Default) COM2, 2F8 IRQ 3 COM3, 2E8 IRQ 3 COM4, 3E8 IRQ 4 Disabled Serial port 2 disabled
This can be used to change the default port address of the onboard parallel (printer) port.
378/IRQ7 Standard LPT1 address (Default) 278/IRQ5 Standard LPT2 address 3BC/IRQ7 Alternate LPT address - NOTE: Cannot use EPP (or ECP+EPP) with this configuration. Disabled Printer parallel port disabled
This allows you to select the operation mode of the onboard printer port.
Normal Standard parallel port mode (Default) EPP Bi-directional mode ECP Fast, buffered EPP/ECP Bi-directional and buffered
The Power Management Setup allows you to configure you system
to most effectively save energy while operating in a manner consistent
with your own style of computer use.
This category allows you to select the type (or degree) of power
saving and is directly related to the following modes:
1. Doze Mode
2. Standby Mode
3. Suspend Mode
4. HDD Power Down
There are four selections for Power Management, three of which
have fixed mode settings.
When enabled, an Advanced Power Management device will be activated
to enhance the Max. Power Saving mode and stop the CPU internal
clock.
If the Max. Power Saving is not enabled, this will be preset to
No.
This determines the manner in which the monitor is blanked.
PM Timers
The following four modes are Green PC power saving functions which
are only user configurable when User Defined Power Management
has been selected. See above for available selections.
When enabled and after the set time of system inactivity, the
CPU clock will run at at slower speed while all other devices
still operate at full speed.
When enabled and after the set time of system inactivity, the
fixed disk drive and the video would be shut off while all other
devices still operate at full speed.
When enabled and after the set time of system inactivity, all
devices except the CPU will be shut off.
When enabled and after the set time of system inactivity, the
hard disk drive will be powered down while all other devices remain
active.
Power Down and Resume events are I/O events whose occurrence can
prevent the system from entering a power saving mode or can awaken
the system from such a mode. In effect, the system remains alert
for anything which occurs to a device which is configured as On,
even when the system is in a power down mode.
The following is a list of IRQ's, Interrupt ReQuests,
which can be exempted much as the COM ports and LPT ports above
can. When an I/O device wants to gain the attention of the operating
system, it signals this by causing an IRQ to occur. When the
operating system is ready to respond to the request, it interrupts
itself and performs the service.
As above, the choices are On and Off. Off is the
default.
When set On, activity will neither prevent the system from
going into a power management mode nor awaken it.
This section describes configuring the PCI bus system. PCI, or
Personal Computer Interconnect, is a system
which allows I/O devices to operate at speeds nearing the speed
the CPU itself uses when communicating with its own special components.
This section covers some very technical items and it is strongly
recommended that only experienced users should make any changes
to the default settings.
The Award Plug and Play BIOS has the capacity to automatically
configure all of the boot and Plug and Play compatible devices.
However, this capability means absolutely nothing unless you
are using a Plug and Play operating system such as Windows 95.
Choices are Enabled and Disabled (default).
A INT# is an interrupt request which is signaled to and
handled by the PCI bus. However, since the operating system usually
has the final responsibility for handling I/O, INT#s can
be mapped to an IRQ if the device occupying a given slot requires
an IRQ service. By default, IRQ's 9 and 10 to PCI are mapped
to PCI devices, but any available, unused IRQ can be used.
You can select which INT# is associated with each PCI slot
and which conventional IRQ is associated with one of the two available
INT#s. The IRQ settings must be the same as the jumper
settings on the motherboard.
A setting of NA means the IRQ has been assigned to the ISA bus
and is not available to any PCI slot.
This sets the method by which the PCI bus recognizes that an IRQ
service is being requested by a device. Under all circumstances,
you should retain the default configuration unless advised otherwise
by your system's manufacturer.
Choices are Level (default) and Edge.
This allows you to configure your system to the type of IDE disk
controller in use. By default, Setup assumes that your controller
is an ISA (Industry Standard Architecture) device rather than
a PCI controller. The more apparent difference is the type of
slot being used.
If you have equipped your system with a PCI controller, changing
this allows you to specify which slot has the controller and which
PCI interrupt (A, B,C or D) is associated with the connected hard
drives.
Remember that this setting refers to the hard disk drive itself,
rather than individual partitions. Since each IDE controller
supports two separate hard drives, you can select the INT# for
each. Again, you will note that the primary has a lower interrupt
than the secondary as described in "Slot x Using INT#"
above.
Selecting "PCI Auto" allows the system to automatically
determine how your IDE disk system is configured.
Copyright © 1996, Award Software International, Inc. All rights reserved.
Triton II Power Management Setup
Power Management
Disable (default) No power management. Disables all four
modes
Min. Power Saving Minimum power management. Doze Mode = 1
hr. Standby Mode = 1 hr., Suspend Mode = 1
hr., and HDD Power Down = 15 min.
Max. Power Saving Maximum power management -- ONLY AVAILABLE
FOR SL CPU'S. Doze Mode = 1 min., Standby
Mode = 1 min., Suspend Mode = 1 min., and
HDD Power Down = 1 min.
User Defined Allows you to set each mode individually.
When not disabled, each of the ranges are
from 1 min. to 1 hr. except for HDD Power
Down which ranges from 1 min. to 15 min.
and disable.
PM Control APM
Video Off Method
V/H SYNC+Blank This selection will cause the system to
turn off the vertical and horizontal
synchronization ports and write blanks to
the video buffer.
Blank Screen This option only writes blanks to the
video buffer.
Doze Mode
Standby Mode
Suspend Mode
HDD Power Down
Power Down & Resume Events
Triton II PCI Configuration Setup
PnP BIOS Auto Config
1st/2nd/3rd/4th Available IRQ
PCI IRQ Activated by
PCI IDE IRQ Map to
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